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Update comments in Teensy_IMXRT.h

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PaulStoffregen 2022-02-25 07:41:36 -08:00
parent e82dba6210
commit 9b05d6a59a
1 changed files with 4 additions and 4 deletions
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8
pinouts/Teensy_IMXRT.h
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@ -1,7 +1,7 @@
#ifndef TLC_Teensy_IMXRT_h #ifndef TLC_Teensy_IMXRT_h
#define TLC_Teensy_IMXRT_h #define TLC_Teensy_IMXRT_h
// bitbang I/O is pretty fast on Teensy 3.1 // bitbang I/O is plenty fast on Teensy 4
// and avoids SPI sharing problems // and avoids SPI sharing problems
#ifdef DATA_TRANSFER_MODE #ifdef DATA_TRANSFER_MODE
#undef DATA_TRANSFER_MODE #undef DATA_TRANSFER_MODE
@ -18,17 +18,17 @@
#define DEFAULT_BB_SCLK_PORT 7 #define DEFAULT_BB_SCLK_PORT 7
#define DEFAULT_BB_SCLK_DDR 7 #define DEFAULT_BB_SCLK_DDR 7
// FTM1_CH0 (Teensy pin 3) -> XLAT (TLC pin 24) // FlexPWM4_2_B (Teensy pin 3) -> XLAT (TLC pin 24)
#define XLAT_PIN 3 #define XLAT_PIN 3
#define XLAT_PORT 3 #define XLAT_PORT 3
#define XLAT_DDR 3 #define XLAT_DDR 3
// FTM1_CH1 (Teensy pin 4) -> BLANK (TLC pin 23) // FlexPWM4_2_A (Teensy pin 2) -> BLANK (TLC pin 23)
#define BLANK_PIN 2 #define BLANK_PIN 2
#define BLANK_PORT 2 #define BLANK_PORT 2
#define BLANK_DDR 2 #define BLANK_DDR 2
// CMTOUT (Teensy pin 5) -> GSCLK (TLC pin 18) // PWM (Teensy pin 5) -> GSCLK (TLC pin 18)
#define GSCLK_PIN 5 #define GSCLK_PIN 5
#define GSCLK_PORT 5 #define GSCLK_PORT 5
#define GSCLK_DDR 5 #define GSCLK_DDR 5