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Teensy 3.1 port, GSCLK working

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PaulStoffregen 2014-06-08 10:45:26 -07:00
parent ba10c7c572
commit 8e4273385f
2 changed files with 64 additions and 28 deletions
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22
Tlc5940.cpp
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@ -66,7 +66,7 @@ static inline void Tlc5940_interrupt(void)
#if defined(__AVR__) #if defined(__AVR__)
ISR(TIMER1_OVF_vect) { Tlc5940_interrupt(); } ISR(TIMER1_OVF_vect) { Tlc5940_interrupt(); }
#elif defined(__avr__) && defined(TEENSYDUINO) #elif defined(__arm__) && defined(TEENSYDUINO)
#endif #endif
@ -101,8 +101,7 @@ void Tlc5940::init(uint16_t initialValue)
clear_pin(VPRG_PORT, VPRG_PIN); // grayscale mode (VPRG low) clear_pin(VPRG_PORT, VPRG_PIN); // grayscale mode (VPRG low)
#endif #endif
#if XERR_ENABLED #if XERR_ENABLED
XERR_DDR &= ~_BV(XERR_PIN); // XERR as input pullup_pin(XERR_DDR, XERR_PORT, XERR_PIN); // XERR as input, enable pull-up resistor
XERR_PORT |= _BV(XERR_PIN); // enable pull-up resistor
#endif #endif
set_pin(BLANK_PORT, BLANK_PIN); // leave blank high (until the timers start) set_pin(BLANK_PORT, BLANK_PIN); // leave blank high (until the timers start)
@ -152,12 +151,25 @@ void Tlc5940::init(uint16_t initialValue)
#endif #endif
TCCR1B |= _BV(CS10); // no prescale, (start pwm output) TCCR1B |= _BV(CS10); // no prescale, (start pwm output)
#elif defined(__avr__) && defined(TEENSYDUINO) #elif defined(__arm__) && defined(TEENSYDUINO)
SIM_SCGC4 |= SIM_SCGC4_CMT;
CMT_MSC = 0;
CMT_PPS = 0;
CMT_CGH1 = TLC_TIMER_TEENSY3_NORMAL_CGH1;
CMT_CGL1 = TLC_TIMER_TEENSY3_NORMAL_CGL1;
CMT_CMD1 = 1;
CMT_CMD2 = 0;
CMT_CMD3 = 0;
CMT_CMD4 = 0;
CMT_OC = 0x60;
CMT_MSC = 0x01;
CORE_PIN5_CONFIG = PORT_PCR_MUX(2)|PORT_PCR_DSE|PORT_PCR_SRE;
#endif #endif
update(); update();
} }
void cmt_isr(void) { uint8_t tmp = CMT_MSC; tmp = CMT_CMD2; }
/** Clears the grayscale data array, #tlc_GSData, but does not shift in any /** Clears the grayscale data array, #tlc_GSData, but does not shift in any
data. This call should be followed by update() if you are turning off data. This call should be followed by update() if you are turning off
all the outputs. */ all the outputs. */

52
pinouts/Teensy_KinetisK20.h
View File

@ -1,23 +1,22 @@
#ifndef TLC_Teensy_xxU4_h #ifndef TLC_Teensy_xxU4_h
#define TLC_Teensy_xxU4_h #define TLC_Teensy_xxU4_h
#if DATA_TRANSFER_MODE == TLC_BITBANG // bitbang I/O is pretty fast on Teensy 3.1
#error "If you want bitbang mode, insert pin defs here" // and avoids SPI sharing problems
#ifdef DATA_TRANSFER_MODE
#undef DATA_TRANSFER_MODE
#endif #endif
#define DATA_TRANSFER_MODE TLC_BITBANG
// MOSI (Teensy pin 11) -> SIN (TLC pin 26) // Teensy pin 6 -> SIN (TLC pin 26)
#define TLC_MOSI_PIN 11 #define DEFAULT_BB_SIN_PIN 6
#define TLC_MOSI_PORT 11 #define DEFAULT_BB_SIN_PORT 6
#define TLC_MOSI_DDR 11 #define DEFAULT_BB_SIN_DDR 6
// SCK (Teensy pin 13) -> SCLK (TLC pin 25) // Teensy pin 7 -> SCLK (TLC pin 25)
#define TLC_SCK_PIN 13 #define DEFAULT_BB_SCLK_PIN 7
#define TLC_SCK_PORT 13 #define DEFAULT_BB_SCLK_PORT 7
#define TLC_SCK_DDR 13 #define DEFAULT_BB_SCLK_DDR 7
// SS (Teensy pin 10)
#define TLC_SS_PIN 10
#define TLC_SS_DDR 10
// FTM1_CH0 (Teensy pin 3) -> XLAT (TLC pin 24) // FTM1_CH0 (Teensy pin 3) -> XLAT (TLC pin 24)
#define XLAT_PIN 3 #define XLAT_PIN 3
@ -34,5 +33,30 @@
#define GSCLK_PORT 5 #define GSCLK_PORT 5
#define GSCLK_DDR 5 #define GSCLK_DDR 5
// Timer settings...
#if F_BUS == 60000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 4
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 11
#elif F_BUS == 56000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 3
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 11
#elif F_BUS == 48000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 3
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 9
#elif F_BUS == 36000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 2
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 7
#elif F_BUS == 24000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 2
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 4
#elif F_BUS == 16000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 1
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 3
#elif F_BUS <= 8000000
#define TLC_TIMER_TEENSY3_NORMAL_CGH1 1
#define TLC_TIMER_TEENSY3_NORMAL_CGL1 1
#else
#error "F_BUS must be 60, 56, 48, 36, 24, 16, 8, 4, or 2 MHz"
#endif #endif
#endif